1. Field of the Invention
The present invention relates to techniques for generating timeout event triggers and, more particularly, to techniques for generating multiple timeout event triggers in response to multiple timeout events.
2. Related Art
In the context of electronic circuitry, the term “timeout event” refers to the failure of a circuit component to perform a task within a particular period of time. One example of a timeout event is the failure of a microprocessor to generate a response to a message received from another microprocessor. Circuits typically include watchdog timers to identify the occurrence of timeout events and to generate timeout signals (also referred to as “timeout event trigger signals” or simply as “triggers”) in response to such events and thereby to signal their occurrence to other circuit components. Timeout event triggers may be provided to a processor or other circuitry so that such circuitry may take appropriate action in response to the timeout event. For example, in response to a timeout event trigger generated by a particular circuit component, a reset signal may be transmitted to the component in an attempt to reset the component and thereby to bring it back into a normal mode of operation. In any particular circuit, there may be a variety of timeout events of varying durations that need to be identified and for which timeout event triggers need to be generated.
Referring to FIG. 1, a schematic diagram is shown of a prior art system 100 including a plurality of circuits 102a-d coupled to a plurality of watchdog timers 104a-d. Both circuits 102a-d and watchdog timers 104a-d are clocked by a common clock 106, which outputs a clock signal on line 120.
Watchdog timer 104a receives the clock signal on line 120 at clock input 110a. Watchdog timer 104a includes a count register 112a that is incremented at each clock cycle. The watchdog timer 104a also includes a control register 114a that contains a timeout threshold value. The watchdog timer 104a also includes a comparator 116a, which compares the contents of the count register 112a and the control register 114a and determines whether they are equal to each other. The comparator 116a asserts a timeout trigger signal on line 118a when the values of the count register 112a and the control register 114a are equal to each other.
During normal operation of circuit 102a, circuit 102a periodically transmits a reset signal to reset input 108a of watchdog timer 104a, thereby causing the value of the count register 112a to be reset. In particular, if thresh is the value of the control register 114a, the circuit 102a should generate a reset signal with a period that is less than thresh during normal operation. The assertion of the trigger signal on line 118a by the watchdog timer 104a therefore indicates that the circuit 102a has not generated a reset signal in at least thresh clock cycles, and that a timeout event therefore has occurred in circuit 102a. 
Watchdog timers 104b-d similarly include reset inputs 108b-d, clock inputs 110b-d, count registers 112a-d, control registers 114a-d, and comparators 116b-d, and similarly generate triggers on lines 118b-d. 
Let t be the number of distinct triggers capable of being generated by the system 100. In the example illustrated in FIG. 1, t=4. Let n be the maximum number of bits required to represent the timeout threshold value stored in any of the control registers 114a-d. For example, if each of the control registers 114a-d is required to store a timeout threshold value (thresh) up to 32000, then n=15, because 15 bits are required to represent values ranging from 0-32000. The size of system 100 scales linearly with the values of t and n. In particular, the widths of the count registers 112a-d, control registers 114a-d, comparators 116a-d, and trigger signals 118a-d increase as the value of n increases, and the number of watchdog timers increases as the value of t increases.
For example, in the case in which t=4 and n=15, four watchdog timers would be required, each of which would be required to include a 15-bit count register, control register, and comparator, for a total of 60 (4*15) count register bits, 60 control register bits, and 60 comparator bits.
The size and expense of such circuitry can become prohibitively large when a large number of triggers having large timeout threshold values are required. What is needed, therefore, are improved techniques for efficiently providing multiple timeout event triggers in an electronic circuit.